Set as default Homepage|Bookmark
» » NI AWR Design Environment 14.04R Build 9307 Rev2 (118446) (x64)

NI AWR Design Environment 14.04R Build 9307 Rev2 (118446) (x64)

Author: wroser on 13-12-2019, 14:47

NI AWR Design Environment 14.04R Build 9307 Rev2 (118446) (x64)
x64 | File Size: 636 MB

Frequencies and high frequencies such as amplifiers, mixers, oscillators, and more. is . AWR Design Environment is one of the specialized telecom group software that is suitable for engineers and students in telecommunications and electronics, as well as all those who work in the field of RF and Microwave circuits. The AWR Design Environment consists of three different tools. The powerful tools are fully integrated in the AWR Design Environment, which makes it impossible to leave the application environment for use during operation. The VSS program enables you to design End-to-End communication systems. Analyze. You can design systems consisting of modulated signals in this section.

The NI AWR Design Environment V14 platform focuses on all stages of RF/microwave design with new features and enhancements to address the challenging component and system performance requirements of next-generation wireless devices, communications and radar systems.

V14 (inclusive of Microwave Office, Analog Office, Visual System Simulator™, AXIEM, and Analyst™ software) is available now and introduces a new network synthesis wizard for impedance matching of multi-band amplifiers and front-end components, advanced design editing/selection for fast EM verification of imported RF/mixed-signal PCBs, as well as the industry's first phased array generation wizard for antenna-array design. Additionally, further enhancements in EM analysis, design flow automation, and usability deliver greater productivity and design success to customers.

Different parts of the software AWR Design Environment:
This section allows you to design and analyze telecommunication systems, channel blocks, coded schemes and simulate them by VSS receivers and transmitters. You can choose, based on the analysis you need, to display the curves of BER, Constellation, power spectra and .... The VSS tuner has the time to adjust the layout and immediately see the effect of the changes.

Microwave Office
This division is made up of two Microwave Office MWO and Microwave Office AO subunits and it is possible to design circuitry combining schematic and magnetic structure with the AWR simulation engine, which includes linear simulators, advanced and nonlinear harmonic simulators, and electromagnetic simulators. Gives you This tool gives you the graphical results of the analysis and allows you to reflect plans directly on the project, according to available reports, optimizations and changes.

3D Planar Electromagnetic (EM) Analysis
This tool allows users to analyze, optimize, and easily describe Passive components in various departments such as RF PCBs, Modules, LTCCs, MMICs, RFICs, Antennas. Using this section, less time is spent on design.

3D FEM Electromagnetic (EM) Analysis
Using this tool, users can view designs drawn by other tools in 3D and, if necessary, optimize and modify design circuits and output data.

Features and Features of AWR Design Environment:
- No need to leave the main program environment
- Design of power amplifiers (rf power amplifier)
- Design, analysis of End-to-End communication systems
- Oscillator design
- Design and simulation of RF circuits and high frequency

System Requirements:
-Windows 10 (x64)
-Windows 8.1 (x64)
-Windows 7 SP1 (x64)

Minimum Hardware:
-64-bit CPU with AVX support
-2+ GB available disk space

Preferred Hardware:
-Best in market CPU (multi-core, 64-bit)
-16+ GB RAM*
-10+ GB available disk space

The NI AWR Design Environment version 14.04 software includes the following new features, enhancements, and user interface changes.

-Environmental options can now be changed via the API when the project is closed.
-Removing a large number of optimization goals from a large project via the API is now much quicker.
-Added Visible and Name properties to the API MaterialLayer object.

Geometry Simplification Rules
-The Shape PreProcessing (SPP) command 'SMALL_CORRECTIONS_SNAP" no longer generates shapes with twisted or jagged outlines.
-Improved the SPP engine, in particular when using the Mask Layer option on filleting commands. Shape vertices are no longer sometimes erroneously considered to be inside a mask region.
-Improved Shape PreProcessing of 3D EM structures used as subcircuits, improving project open times.
-Improved performance speed of SPP operations in layouts that contain many small shapes to be resized and operated on.

-Changing a graph type from rectangular to a type that doesn't support vertical line markers (for example, a histogram) when the graph has a vertical line marker that is selected no longer causes a crash.
-Markers displaying VSS RF Budget Analysis measurements no longer display the text describing the measurements, but only the information pertaining to the measured values and swept values, providing a more compact display.

Job Scheduler
-Job Scheduler service no longer needs to be restarted on remote machines to recognize new features when a license file is changed.

-The Layout window now correctly zooms to a single segment DRC error when clicking on the error.
-Fixed an issue in which Undo of an MLIN layout element width change not return back to the original size.
-Undo operations on pCell objects which constrain stretch operations now correctly restore the cell to its previous state.
-Using a short segment in an iNet path bend no longer results in a self-intersecting polygon which renders incorrectly.
-Parameterized subcircuits using a different process definition (LPF) from the top level design no longer sometimes draw shapes with incorrect layers.
-In designs with the dynamic highlight layer set to non-visible, area selection animation now works consistently.
-GSDII export of complex polygon shapes with merged positive and negative layers, and a large number of holes now functions correctly.
-Improved the speed of the Remove Cutlines command on layouts with a large number of cutlines.
-Polygons abutting each other are now properly unioned when Cutout processing is set to Retain holes for cutouts on the Layout Options dialog box Boolean tab.

-Using the Copy to Arbitrary 3D EM Structure command on an Analyst structure that has an invalid port type now just prompts an error message.
-Analyst lumped port extensions no longer extend beyond the bottom enclosure when attached to a EM subcircuit that references the bottom enclosure for its z-position.
-Analyst re-simulations now consistently occur when moving an internal wave port.
-A 3D EM part that is flipped in the x-axis and rotated around the y-axis is now oriented correctly in the Preview Geometry 3D Layout View.
-When adding a cut plan in a 3D View, the initial view now exposes the interior of the geometry from the viewer's perspective.

-Artwork cells can now be sorted alphabetically in the Cell Library pane of the Layout Manager by clicking on the Name column header.

Measurements - System
-The RFA_TDF measurement now applies a tolerance for noise factor values near 1, thereby avoiding generating negative noise figure values because the round-off errors had resulted in a noise factor just under 1.
-The available gain reported by C_GA is now correct for reversible RF linear blocks if they are reversed and are non-symmetric (the gain in one direction is different from the gain in the opposite direction).
-When using the C_GA measurement with an RF linear block with multiple input ports, if the input port for the C_GA measurement is not along the path to the primary input port of the RF linear block, gain is now correctly reported. Note that the branching limitations of the C_GA measurements are still present.

Models - Circuit
-Improved APLAC simulation of the BSIMSOI model.
-HSPICE netlist import of the BSIMSOI model now functions correctly.

Models - System
-The DIFF block may now be used in RF Budget Analysis and RF Inspector simulations for voltage subtraction. Note that the block is not a true RF block and therefore does not fully model noise nor impedance mismatch.
-If a mixer's LO is connected in a feedback loop to the mixer's output, a time domain simulation can now be run again without reporting an LO center frequency of 0 error.

Schematic Editor
-A variable entered for a FILE parameter value in an Element Options dialog box is now recognized as variable.

-The Archive Project script now handles locked schematics properly.
-The Generate_MDIF_Files script now handles larger S-parameter files.

Simulation - Analyst
-Analyst arbitrary 3D structures are now saved correctly when the file path contains double-byte characters.

Simulation - APLAC
-Thermal nodes are now skipped when computing DC power consumption with a PAE measurement. A thermal node is one having a TNODE element connected to it.
-Optimization of measurements on APLAC simulations involving multiple EXTRACT blocks and extracted EM documents no longer fails.

Simulation - AXIEM
-AXIEM no longer has passivity issues caused by closely located explicit edge ports on different layers with ground extensions that connect from top and bottom to the same thick metal internal ground plane that separates the ports.

Simulation - Extraction
-Extraction ports in a schematic no longer sometimes cause EM ports to have the wrong Pin_ID in the extracted EM structure.

Simulation - Systems
-Running Time Domain simulations when the OVFLTYP parameter of a test point is set to "Lose Newest" no longer causes access violations.
-The EVM_PS measurement now displays the correct results for "Final Output Type" set to "Average" or "Peak". It correctly accounts for Output Length when defined in "Blocks". The summary information displayed when the trace is clicked now includes the number of blocks, the average EVM, and the peak EVM, in both percent and dB.
-Reducing the maximum number of components generated per block in RF Inspector simulations no longer sometimes results in the loss of frequency components that should have been retained.

Tuning, Yield Analysis, and Optimization
-Invalid limits can no longer be entered when tuning enumerated values.
-Error states in the Optimizer are now being stored correctly. Reverting to the error state now works properly.
-The Tuner lower and upper limits now update immediately when the limits are changed for equation variables.
-The Tuner Restore and Save commands no longer remain disabled after changing Element values.

User Interface
-CTRL- or SHIFT-selection of multiple netlists for simultaneous import is now available.

Wizards - Create New Process Tool
-Application of changes to a Layer line and fill pattern or color is no longer prevented.

Wizards - IFF Import/Export
-Importing capacitance values with units set to "F" from ADS now functions correctly.

Wizards - Network Synthesis
-Added support for source-pull data in the Network Synthesis Wizard.
-Infinite loops no longer sometimes occur when running the Network Synthesis Wizard with a load-pull goal.
-In the Network Synthesis Wizard, synthesizing with a relatively large maximum number of sections no longer causes a crash.
-Double-clicking on the results grid in the Network Synthesis Wizard when no results are present no longer causes a crash.

Wizards - OpenAccess Import/Export
-Modified the OpenAccess Import/Export Wizard to allow space characters in the default value for parameters in the element map file.

Wizards - PCB Import
-In IPC-2581 file imports, paths with sharp bends are no longer imported with missing segments.

Wizards - Phased Array Generator
-In the Phased Array Generator wizard, lattice taper is now correctly applied to Custom geometry that is specified as a lattice.

NI AWR Design Environment 14.04R Build 9307 Rev2 (118446) (x64)


NI AWR Design Environment 14.04R Build 9307 Rev2 (118446) (x64)

Теги: NI

Dear visitor, you are browsing our website as Guest.
We strongly recommend you to register and login to view hidden contents.


Add Comments